Increasingly complex functions are being implemented in ASIC and field programmable gate arrays (FPGAS) given recent advances in silicon technology. Design trends are shifting toward system-level integration in order to reduce the time-to-market and reduce development costs.
System-level integration relies on reuse of previously created designs, either from within an enterprise or from a commercial provider. The engineering community sometimes refers to these previously created designs as “design modules”, “cores” or “IP” (intellectual property). As on-chip processors and large functional blocks become increasingly common, vendors are making complex design modules available for general usage, and companies are making modules for reuse within the respective organizations. These design modules are then integrated into larger systems by end-users.
For reusable design modules to be successful, they must be easy to use. Design modules that are amenable to reuse must be well documented, possess sufficient parameterization, have an understandable structure, follow certain coding guidelines, and be extensible for future usage. Reusable design modules should also have a well-planned and documented testbench. To varying degrees, many commercial and internal design modules satisfy these objectives. However, the process and tools used to create a design module will often limit the ease and extent to which the objectives can be satisfied.
A method that address the aforementioned problems, as well as other related problems, is therefore desirable.